EE3207Digital System Design

What you will study

Course overview

Learn digital-system design methods using a hardware description language (HDL), with prototyping on FPGA devices.

Official PDF, page 2 · Abstract

Course content

Digital-system design concepts; Verilog; sequential logic; logic synthesis; FPGA realization; register-transfer-level methodology; asynchronous sequential logic.

Official PDF, page 6 · Keyword Syllabus

Laboratory experiments

Four labs: EDA tools and FPGA rapid prototyping; combinational-circuit modeling with HDL; sequential-circuit modeling with HDL; and an RTL digital-system design mini-project.

Official PDF, page 6 · Laboratory Experiment

Intended learning outcomes

View learning outcomes

CILO	Intended learning outcome	Weight	DEC
1	Demonstrate basic knowledge of HDL.	—	—
2	Apply HDL to model combinational and sequential digital circuits.	—	—
3	Design digital systems at register-transfer level.	—	—
4	Use EDA tools for circuit modeling, simulation, functional verification and FPGA prototyping.	—	—

Official PDF, page 2 · Course Intended Learning Outcomes (CILOs)

Before you take this course

Check prerequisites, precursors and corequisites separately, together with equivalence and exclusion conditions. “and” means conditions must be met together; “or” marks alternatives. Read combined conditions in the groupings shown in the original text below.

Prerequisites

EE2000 Logic Circuit Design

Official PDF, page 1 · Prerequisites

Precursors

Nil

Official PDF, page 1 · Precursors

Corequisites

Complete official information for this field is not available.

Additional course requirements

Complete official information for this field is not available.

Equivalent courses and conditions

Nil

Official PDF, page 1 · Equivalent Courses

Exclusive courses and conditions

Nil

Official PDF, page 1 · Exclusive Courses

Assessment and passing the course

Assessment

Continuous assessment: 40% (assignments 10%, quizzes/midterms 20%, laboratory demonstrations/formal reports 10%); examination: 60% (2 hours). Pass condition: at least 30% in coursework and examination, plus 75% laboratory attendance.

Assessment breakdown

Assessment task	Weight	Generative AI	Remarks and restrictions
Assignments (at least 3)	10%	Not stated in source	Not stated in source row
Quizzes and midterms	20%	Not stated in source	Not stated in source row
Laboratory demonstrations and formal reports	10%	Not stated in source	Not stated in source row

Official PDF, page 3 · Assessment Tasks/Activities

Passing requirements

At least 30% in coursework and at least 30% in the examination; laboratory attendance of at least 75%.

Official PDF, page 3 · Remark